1. Field of the Invention
The present invention relates generally to a design aiding apparatus, method, and computer program for aiding in a layout design of elements on a multilayer wiring board. In particular, the present invention relates to technology that aids in the placement of the elements on the wiring board so as to reduce noise.
2. Related Art
A prior art design aiding apparatus used in the layout design of elements such as components, wiring foils, and vias on a multilayer wiring board (i) stores various design criterion information that shows manufacturing restrictions relating to the processing of boards, the mounting of components, and the like, (ii) automatically determines the placement area of the various elements so as to comply with the design criterion information, and (iii) reports when the placement area of an element as indicated by a designer does not comply with the design criterion information.
The design criterion information includes such information as (i) the minimum distance allowable between wiring foils, components, component pads (i.e. the connection area between wiring foil and component), and via pads (i.e. the connection area between via and wiring foil), and (ii) the minimum distance allowable between the various wiring elements (i.e. wiring foils, components, component pads, via pads) and the edge of the board.
FIG. 27 shows an exemplary clearance information table 480 provided in the prior art design aiding apparatus to store information showing the minimum distances described above. Table 480 has a first classification row 481, a second classification column 482, and clearance value cells 483 that store values showing the spacing to be provided between the various elements given in row 481 and column 482.
In the prior art design aiding apparatus, the placement of wiring foils, components, component pads, and via pads is determined automatically by component placement processing and wiring processing so as satisfy the minimum distances stored in clearance information table 480.
The prior art design aiding apparatus also stores the minimum distances required between the various layers of the board (i.e. the power layer and the signal line layers provided above and below the power layer) in order to achieve a predetermined level of noise reduction, and wiring is conducted automatically in accordance with these stored minimum distances. The technology relating to the automatic wiring of multilayer wiring boards is disclosed in unexamined patent application publication 11-328235 “Pattern Automatic Wiring Method” filed in Japan.
Application of the prior art design aiding apparatus and the automatic wiring method serves to reduce the workload required of the designer in the layout design of components, foils and other elements on a multilayer wiring board, and as a result, reductions in design time and cost can be achieved.
However, research conducted in recent years into current flow in multilayer wiring boards has revealed a previously unknown cause of electromagnetic interference (EMI). It is now known that EMI is increased by current flowing through components, foils, and other elements whose placement area, as seen in a lamination direction of the board, overlaps with perimeter areas of the power plane and ground plane having a predetermined margin. This is particularly true of current that has a large high frequency component.
An effective means of reducing EMI caused by such current is to place the various elements so that, as seen in the lamination direction of the board, they are included within an area of the power and ground planes excluding a perimeter area having a predetermined margin.
This approach to reducing EMI is disclosed in Mark I. Montrose's Printed Wiring Board Design Techniques for EMC Compliance, IEEE Press, 2nd ed.2000, (order no. PC5816).
However, the prior art design aiding apparatus and automatic wiring method do not include design criterion information or design aiding capabilities that allow for the placement area of elements to be determined such that the elements, as seen in the lamination direction of the board, are included within an area of the power and ground planes excluding a perimeter area.
In order to reduce the occurrence of EMI as described above, the designer is consequently required to manually determine the placement of the various elements, and as a result, the time and cost required in implementing layout design that takes account of the effects of EMI cannot be reduced.